18.1EP.05 - PROBABILITY OF LATENT FAILURES CAUSED BY ELECTRO-STATIC DISCHARGE (ESD) TESTING

Publication Date: 28-JUN-18

Program ref.: Technology Developme
Tender Type: C
Tender Status: INTENDED
Price Range: > 500 KEURO
Budget Ref.: E/0901-01 - Technology Developme
Proc. Prop.: DIPC
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Engineering Department
Division: RF Payloads & Technology Division
Products: Satellites & Probes / Electronics / EEE Components / Capacitors Satellites & Probes / Electronics / EEE Components / Connectors Satellites & Probes / Electronics / EEE Components / Discrete semiconductors (including diodes, transistors) Satellites & Probes / Electronics / EEE Components / Filters Satellites & Probes / Electronics / EEE Components / Resistors, heaters
Techology Domains: Spacecraft Environments and Effects / Environment Effects / Ground and Space Effects Investigations Electromagnetic Technologies and Techniques / EMC/RFC/ESD / EMC Modelling and Simulation Electromagnetic Technologies and Techniques / EMC/RFC/ESD / EMC Test Techniques EEE Components and Quality / Methods and Processes for Product Assurance of EEE Components, including Radiation Hardness Assurance / Evaluation and Testing Materials and Processes / Materials for Electronic Assembly / Verification of Electronic Assemblies
Industrial Policy Measure: N/A - Not apply

ESD testing is generally carried out to verify that an equipment is adequately protected against the effects of a high voltage discharge, e.g. due to electric charge build-up. When a test discharge is applied to the equipment under test (EUT) effects are typically seen immediately: the equipment may (or may not) be damaged by the discharge. Expected immediate failures at unit level (if any) are for example data corruption, signal acquisition glitches or changes in the operating mode like register bit flips. If even permanent damage occurs, the designer has to rework the design to improve the ESD protection. The test method can provide also a convenient and fast test to detect unexpected vulnerability to electromagnetic fields induced by workmanship or manufacturing defects. However, one of the most controversial issues is the probability of this test to cause latent damage to electronic components in integrated systems, such as PCBs, breadboards or units. Instead of immediate failure or damage, the additional stress on components could forexample significantly increase parameter drifts which would lead to a premature failure. Therefore ESD testing of flight hardware is at present forbidden by ECSS standards (ECSS-E-ST-10-03 and ECSS-E-ST-20-07). The probability of these failures, however, has not been quantified yet. The degradation of parameters and/or increased parameter drift is reported and discussed in literature typically at component level, but especially for state-of-the art technology studies are missing at higher integration level, e.g. for units. Moreover complete information on data and test conditions is rarely available to perform a solid assessment. The situation is further complicated, because there are a number of 'models' of ESD used for testing, with varying rise-times, charge capacitance and resistance, energy, and discharge voltage, depending on the application. The model used to simulate ESD for commercial, household and light industrial specifications is different to that used by automotive industry, which is different again to those used by space industry. If research shows that the probability of latent damage due to testing with the space industry ESD models is not significant,then substantial savings in time and money can be made by performing ESD testing on Flight Model (FM) or Proto-Flight Model (PFM) units. In a first phase the phenomenon has to be studied together with possible test methodology, protocols and procedures. Successful completion will then allow to proceed with actual testing and statistical analysis of results to be carried out in a second phase.To obtain relevant results for this activity the experience and knowledge of TEC-QTC on components and related lifetime tests will be combined with TEC-EEE expertise on unit-level ESD testing to make the bridge between low-level component effects and high-level ESD unit tests. Activity Outline: Phase A 1) Select an ESD envelope model representative for space applications. 2) Study available literature for involved physical processes at component level and at higher integration levels and define the integration level at which to apply the pulses (PCB, mock-up, or unit level). 3) Study typical interface circuit design to select representative group of components. 4) Consolidate the test approach, e.g. test levels, duration, frequency of repetitions, method of pulse application. 5) Define required variety of components, quantity of each component, etc. based on statistical methods. Phase B 1) Apply discharges in conjunction with other environmental stresses (e.g. heat, cold, shock, vibration, etc.) on a representative group of components withrelevant quantities as derived in Phase A and use a control group of identical components in identical environmental conditions as the test group, but not subjected to any ESD pulses. 2) Disintegrate components and verify relevant parameters over time similar to standard component-level testing, e.g. with accelerated lifetime test.

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